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[Other] statemachine11.2

Description: 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
Platform: | Size: 1854 | Author: 陶玉辉 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_5_10

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 4773 | Author: 丁谨 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_8_23

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 6502 | Author: 丁谨 | Hits:

[Other resource] pipe

Description: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Platform: | Size: 5356 | Author: 刘陆陆 | Hits:

[Program doc] firfilter14

Description: 用Quartus II实现综合布线，要求充分利用Altera Stratix/Stratix II的器件的DSPBLOCK资源，Quartus II综合出的系统最高工作频率达到270Mhz以上.用Verilog进行编程。-Pipeline FIR structure。
Platform: | Size: 2048 | Author: 卢大成 | Hits:

[VHDL-FPGA-Verilog] adder16_2

Description: 16位2级流水线加法器的Verilog设计-16 2 pipeline adder Verilog Design
Platform: | Size: 1024 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] gcd_performence

Description: 基于流水线设计的性能优先的gcd算法的verilog 代码 频率可达500M-based pipeline design gcd for high clock
Platform: | Size: 3072 | Author: youyou | Hits:

[VHDL-FPGA-Verilog] DataMemory

Description: datamemory code in verilog for pipeline processor
Platform: | Size: 1024 | Author: kallu | Hits:

[VHDL-FPGA-Verilog] dp

Description: datapath code in verilog for pipeline processor
Platform: | Size: 1024 | Author: kallu | Hits:

[VHDL-FPGA-Verilog] InstMemory

Description: instruction memory code in verilog for pipeline processor
Platform: | Size: 1024 | Author: kallu | Hits:

[VHDL-FPGA-Verilog] 4add

Description: verilog 实现两级流水线加法器 源代码 以及测试代码 adder16_2.v test_adder16_2.v-verilog Implement two pipeline adder source code and test code adder16_2.v test_adder16_2.v
Platform: | Size: 1024 | Author: keyCSky | Hits:

[VHDL-FPGA-Verilog] DLX-pipeline-in-verilog

Description: verilog实现DLX指令集5段流水线-5 stage DLX pipeline implemented in verilog
Platform: | Size: 915456 | Author: 陈祥 | Hits:

[VHDL-FPGA-Verilog] 8-point-pipeline-fft-by-verilog.pdf

Description: 简单的8位基2 流水 fft verilog-Simple 8 base 2 pipelined fft verilog
Platform: | Size: 220160 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] pipeline

Description: 使用VERILOG實現MIPS2000的PIPELINE-Use VERILOG realized MIPS2000 the PIPELINE
Platform: | Size: 2048 | Author: opgp | Hits:

[VHDL-FPGA-Verilog] pipeline

Description: 简单的流水线的实现机制，基于verilog语言。-The pipelined implementation, based on Verilog language.
Platform: | Size: 1024 | Author: mxc | Hits:

[VHDL-FPGA-Verilog] Cordic-arithmetic-pipeline

Description: FPGA实现基于Cordic算法的流水线结构设计，相关verilog语言代码-FPGA to realize the Cordic code
Platform: | Size: 229376 | Author: 孙永林 | Hits:

[VHDL-FPGA-Verilog] CPU_Verilog

Description: 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
Platform: | Size: 12288 | Author: fairchildfzc | Hits:

[VHDL-FPGA-Verilog] highperformance

Description: 最大公约数（GCD）stein算法实现，高性能流水线实现(The greatest common divisor (GCD) stein algorithm, high performance pipeline implementation.)
Platform: | Size: 2048 | Author: BetaGo | Hits:

[VHDL-FPGA-Verilog] pipelines

Description: 将组合逻辑系统地分割，并在各个部分之间插入寄存器，并暂存中间数据的方法。 将一个大操作分解成若干的小操作，每一步小操作的时间较小，所以能提高频率，各小操作能并行执行，所以能提高数据吞吐率。(A method to divide the combined logical system into a register and temporarily store the intermediate data between the parts. A large operation is decomposed into a number of small operations, each small operation time is small, so can increase the frequency, each small operation can be executed in parallel, so can improve the data throughput rate.)
Platform: | Size: 10240 | Author: 小李子公公 | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: Booth乘法器是属于位操作乘法器，采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.)
Platform: | Size: 2138112 | Author: wlkid1412 | Hits:
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